Latch-up Reduction Output Driver and Latch-Up Reduction Method in CMOS (CMOS) Circuits

摘要

The present invention relates to a latch-up reduction output driver and a latch-up reduction method of a CMOS circuit that minimizes latch-up. P-channel transistor 14 has its source-drain path connected in series with the source-drain path of one or more N-channel transistors 16,12. The internally generated high voltage VCCP higher than VCC is applied to the region 32 where the P-channel transistor 14 is formed, i. E., To the moat or well and also to the gate electrode 26, do. In an embodiment (FIG. 3), the source electrode 34 of the P-channel transistor 14 is connected directly to VCC, but in other embodiments (FIGS. 1a and 1b) 3 4 are connected to the source-drain path of another N-channel transistor 12 and the gate electrode 26 of this N-channel transistor 12 is connected to the high voltage VCCP. In this second embodiment, the drain electrode 24 of the other N-channel transistor 12 is connected to VCC such that a P-channel transistor is placed in series between the two N-channel transistors 12,16 do. One of the N-channel transistors 12 and 16 always supplies a high voltage VCCP (shown in FIG. 1A) or a corresponding reverse voltage (shown in FIG. 1B) to the gate electrode 26, /RTI