An output driver for a CMOS circuit minimizes latch-up. A P-channel transistor (14) has its source-drain path coupled in series with the source-drain path of one or more N-channel transistors (16, 12). An internally generated high voltage VCCP, higher than VCC, is applied to the moat, well, or region (32) in which the P-channel transistor (14) is formed, and is applied to the gate electrode (26, 42) of the N - channel transistor(s). In one embodiment the source electrode (34) of the P-channel transistor (14) is connected directly to VCC whereas in another embodiment , it is coupled to the source-drain path of another N-channel transistor (12), the gate electrode (26) of which is coupled to the high voltage VCCP. In such second embodiment, the drain electrode (24) of the other N-channel transistor (12) is coupled to VCC, so that the P-channel transistor is in series between the two N-channel transistors (12,16). One of the N-channel FETs (12, 16) may receive at its gate electrode (26, 42) either a constant high voltage (VCCP) despite changes in the logic state of the data input signal, or it may correspond inversely therewith.
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