Current Estimation for Electromigration, Hot Carriers, and Voltage Drop

摘要

This report summarizes work in reliability analysis in VLSI CMOS circuits,particularly electromigration in metal lines, power busses and signal lines, hot carrier effects in devices, and voltage drop in power busses. In addition to process parameters, all of these effects can be shown to depend on current flow in the circuit. More specifically, electromigration and hot carrier induced degradation are both long-term effects and are related to the average current flow over time under all possible input signals that the design experiences. Maximum voltage drop, on the other hand, depends on finding the maximum current flow in the power busses, caused by a specific few inputs. Thus, our emphasis in this work is on developing fast and reliable methods for estimating average and maximum currents. In addition, we have also improved on our bus extractor to extract accurate RC models of power busses from layout information for electromigration and voltage drop estimation. This work is part of our goal of developing CAD tools for estimating physical reliability effects in VLSI designs, and to automatically modify the design, or at least suggest design changes, in order to improve the short and long term reliability of the design under realistic operating conditions. Electromigration, Power busses, VLSI CMOS Circuits.