Four ways to reduce voids in BGA/CSP package to substrate connections

摘要

Voids in BGA/CSP package to substrate connections can cause issues with thermal management, drop shock resistance and signal interference. Zero voids are always the best solution, but this is not always easy to achieve. Solder paste printing, reflow, alloy and flux chemistry all have significant influences on the amount of voiding one can expect in an assembly. This paper will discuss how print volume (stencil design), peak reflow temperature, paste flux chemistry and alloy selection affect the level of voiding to be expected when BGA/CSP packages are assembled in a lead free process.