Contoured Device Sample Preparation for ±5 μm Remaining Silicon Thickness (RST) Tolerances

摘要

In the case of both flip-chip and 3-D packages, extreme differences in the coefficients of thermal expansion between the device-package-underfill interfaces cause the silicon or package substrate to bow anywhere from 10 to 150 pm or more (typically convex or concave, respectively, as shown in Fig. la and b). Papers have been written about how to prepare devices using mechanical, chemical, and laser techniques and, more specifically, using a flat-top methodology with some success; 01 however, most failure analysis labs deal with a high variability of devices, and the time to characterize all possible devices is not practical. Additionally, these traditional silicon-thinning sample-preparation techniques typically involve a "flat-top" grinding/polishing process that does not account for the device bow. As a result, the remaining silicon thickness is nonuniform, limiting the effectiveness of electrical fault isolation tools, especially tools using high-numerical-aperture (NA) solid immersion lens (SIL) imaging capabilities.