Improvement of Capacitance Equivalent Thickness, Leakage Current, and Interfacial State Density Based on Crystallized High-K Dielectrics/Nitrided Buffer Layer Gate Stacks

摘要

The gate stack composed of tetragonal/cubic ZrO_2 high-K dielectrics and nitrided Al_2O_3 buffer layer was investigated to reduce the capacitance equivalent thickness (CET), leakage current density (Jg), and interfacial state density (D_(it)). The high-K tetragonal/cubic phase of ZrO_2 was formed by post metallization annealing at a low temperature of 450°C. The J_g was suppressed by the insertion of the Al_2O_3 buffer layer between ZrO_2 and Si. The remote NH3 plasma nitridation on the Al_2O_3 buffer layer further leads to the deactivation of the oxygen vacancies and the well passivation of the Si dangling bonds. Accordingly, a suppressed J_g of 8.12 x 10~(-6) A/cm~2 and D_(it), of 2.77 x 10~(11）cm~（-2）eV~（-1）were achieved in the crystallized ZrO_2itrided Al_2O_3 gate stack with a low CET of 1.2 nm. The gate stack was also optically probed through the photoluminescence from Si, revealing that the hydrogen passivation and depassivation effects caused by the remote NH3 plasma treatment are highly correlated with the D_(it). The results indicate that the crystallized high-K dielectricsitrided buffer layer is a promising gate stack structure to improve the electrical characteristics in the advanced metal-oxide-semiconductor devices.