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首页> 外文期刊>Journal of Semiconductors >Influence of back-gate stress on the back-gate threshold voltage of a LOCOS-isolated SOI MOSFET
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Influence of back-gate stress on the back-gate threshold voltage of a LOCOS-isolated SOI MOSFET

机译:背栅应力对LOCOS隔离SOI MOSFET背栅阈值电压的影响

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摘要

The performance of a LOCOS-isolated SOI MOSFET heavily depends on its back-gate characteristic,which can be affected by back-gate stress. A large voltage stress was applied to the back gate of SOI devices forat least 30 s at room temperature, which could effectively modify the back-gate threshold voltage of these devices.This modification is stable and time invariant. In order to improve the back-gate threshold voltage, positive substratebias was applied to NMOS devices and negative substrate bias was applied to PMOS devices. These results suggestthat there is a leakage path between source and drain along the silicon island edge, and the application of large backgatebias with the source, drain and gate grounded can strongly affect this leakage path. So we draw the conclusionthat the back-gate threshold voltage, which is directly related to the leakage current, can be influenced by back-gatestress.
机译:隔离LOCOS的SOI MOSFET的性能在很大程度上取决于其背栅特性,该特性会受到背栅应力的影响。在室温下,对SOI器件的背栅施加至少30 s的大电压应力,可以有效地修改这些器件的背栅阈值电压,这种修改是稳定的且随时间变化的。为了改善背栅阈值电压,将正衬底偏压施加到NMOS器件,并将负衬底偏压施加到PMOS器件。这些结果表明,沿着硅岛边缘的源极和漏极之间存在泄漏路径,并且源极,漏极和栅极接地的大反向栅偏压的应用会严重影响该泄漏路径。因此,我们得出的结论是,与漏电流直接相关的背栅阈值电压会受到背栅应力的影响。

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