Threshold voltage sensitivity of 0.1 /spl mu/m channel length fully-depleted SOI NMOSFET's with back-gate bias

摘要

We found threshold voltage sensitivity to silicon thickness variation in 0.1 /spl mu/m channel length fully-depleted SOI NMOSFET's can be reduced with lightly-doped channel and back-gate bias. However, after the back-interface is accumulated, the reduction is small and threshold voltage roll-off due to high drain bias increases.