A methodology and design tools to support system-level VLSI design

摘要

System-level design involves making major design decisions withoutnhaving accurate information on the eventual system characteristics. Thisnpaper presents a novel constraint-driven methodology to supportnsystem-level design. The software assists a designer or a tool innpartitioning behavioral specifications onto multiple VLSI chips and innsystem design while satisfying hard constraints such as individual chipnareas, chip pin counts, system throughput (inverse of system initiationninterval) and system latency (delay). The software uses search andnestimation techniques to perform comprehensive design-space explorationnand evaluates partitions supplied by the user or by other synthesisnsoftware. The technique determines what design characteristics eachnpartition must possess in order to satisfy area, pin, throughput andnlatency constraints. The paper also includes results of extensivenexperiments with the methodology