Differential BiCMOS logic circuits: fault characterization and design-for-testability

摘要

Merged Current Switch Logic (MCSL) and Differential Cascode Voltage Switch Logic (DCVSL) are two common structures for differential BiCMOS logic family, that have several potential applications in high-speed VLSI circuits. This paper studies the fault characterization of these BiCMOS circuits. The impact of each possible single defect on the behavior of the circuits is analyzed by simulation. A new class of faults which is unique to differential circuits is identified and its testability is assessed. We propose a design-for-testability method that facilitates testing of this class of faults. Two different realizations for this method are introduced. The impact of this circuit modification on the behavior of the circuit in normal mode is investigated.