Differential BiCMOS logic circuits: fault characterization anddesign-for-testability

摘要

Merged Current Switch Logic (MCSL) and Differential CascodenVoltage Switch Logic (DCVSL) are two common structures for differentialnBiCMOS logic family, that have several potential applications innhigh-speed VLSI circuits. This paper studies the fault characterizationnof these BiCMOS circuits. The impact of each possible single defect onnthe behavior of the circuits is analyzed by simulation. A new class ofnfaults which is unique to differential circuits is identified and itsntestability is assessed. We propose a design-for-testability method thatnfacilitates testing of this class of faults. Two different realizationsnfor this method are introduced. The impact of this circuit modificationnon the behavior of the circuit in normal mode is investigated