Algorithm-based low-power transform coding architectures: themultirate approach

摘要

In most low-power VLSI designs, the supply voltage is usuallynreduced to lower the total power consumption. However, the device speednwill be degraded as the supply voltage goes down. In this paper, wenpropose new algorithmic-level techniques to compensate the increasedndelays based on the multirate approach. We apply the technique ofnpolyphase decomposition to design low-power transform codingnarchitectures, in which the transform coefficients are computed throughndecimated low-speed input sequences. Since the operating frequency isnM-times slower than the original design while the system throughput ratenis still maintained, the speed penalty can be compensated at thenarchitectural level. We start with the design of low-power multiratendiscrete cosine transform (DCT)/inverse discrete cosine transform (IDCT)nVLSI architectures. Then the multirate low-power design is extended tonthe modulated lapped transform (MLT), extended lapped transform (ELT),nand a unified low-power transform coding architecture. Finally, wenperform finite-precision analysis for the multirate DCT architectures.nThe analytical results can help us to choose the optimal wordlength forneach DCT channel under required signal-to-noise ratio (SNR) constraint,nwhich can further reduce the power consumption at the circuit level. Thenproposed multirate architectures can also be applied to very high-speednblock discrete transforms in which only low-speed operators are required