In most low-power VLSI designs, the supply voltage is usually reduced to lower the total power consumption. However, the device speed will be degraded as the supply voltage goes down. In this paper, we propose new algorithmic-level techniques to compensate the increased delays based on the multirate approach. We apply the technique of polyphase decomposition to design low-power transform coding architectures, in which the transform coefficients are computed through decimated low-speed input sequences. Since the operating frequency is M-times slower than the original design while the system throughput rate is still maintained, the speed penalty can be compensated at the architectural level. We start with the design of low-power multirate discrete cosine transform (DCT)/inverse discrete cosine transform (IDCT) VLSI architectures. Then the multirate low-power design is extended to the modulated lapped transform (MLT), extended lapped transform (ELT), and a unified low-power transform coding architecture. Finally, we perform finite-precision analysis for the multirate DCT architectures. The analytical results can help us to choose the optimal wordlength for each DCT channel under required signal-to-noise ratio (SNR) constraint, which can further reduce the power consumption at the circuit level. The proposed multirate architectures can also be applied to very high-speed block discrete transforms in which only low-speed operators are required.
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