Interleaving buffer insertion and transistor sizing into a singleoptimization

摘要

This work presents strategies to insert buffers in a circuit,ncombined with gate sizing, to achieve better power delay and area-delayntradeoffs. The purpose of this work is to examine how combining a sizingnalgorithm with buffer insertion will help us achieve better area delaynor power-delay tradeoffs, and to determine where and when to insertnbuffers in a circuit, The delay model incorporates placement-basedninformation and the effect of input slew rates on gate delays. Thenresults obtained by using the new method are significantly better thannthe results given by merely using a TILOS-like gate sizing algorithmnalone, as is illustrated by several area delay tradeoff curves shown innthis paper