A Post-Layout Optimization by Combining Buffer insertion and Transistor Sizing

摘要

This paper presents methods of combining buffer insertion and transistor sizing into a single post-layout op- timization. The proposed method considers the tradeoff between upsizing transistors and inserting buffers then chooses the solu- tion with the lowest possible poser and area cost. The Proposed method is efficient and tunable in that optimality can be traded for compute time.