Clocked CMOS adiabatic logic with integrated single-phasepower-clock supply

摘要

The design and experimental evaluation of a clocked adiabaticnlogic (GAL) is described in this paper. CAL is a dual-rail logic thatnoperates from a single-phase AC power-clock supply. This new low-energynlogic makes it possible to integrate all power control circuitry on thenchip, resulting in better system efficiency, lower cost, and simplernpower distribution. CAL can also be operated from a DC power supply in annonenergy-recovery mode compatible with standard CMOS logic. In thenadiabatic mode, the power-clock supply waveform is generated using annon-chip switching transistor and a small external inductor between thenchip and a low-voltage DC supply. Circuit operation and performance arenevaluated using a chain of inverters realized in a 1.2 Μm CMOSntechnology. Experimental results show that energy savings are achievednat clock frequencies up to about 40 MHz as compared to the nonadiabaticnmode. Since CAL can operate both in adiabatic and nonadiabatic modes,npower management strategies may be based upon switching between modesnwhen necessary