Exploiting the on-chip inductance in high-speed clock distributionnetworks

摘要

On-chip inductance effects can be used to improve the performancenof high-speed integrated circuits. Specifically, inductance improves thensignal slew rate (the rise time), virtually eliminates short-circuitnpower consumption and reduces the area of the active devices andnrepeaters inserted to optimize the performance of long interconnects.nThese positive effects suggest the development of design strategies thatnbenefit from on-chip inductance. An example of a clock distributionnnetwork is presented to illustrate the process in which inductance cannbe used to improve the performance of high-speed integrated circuits