Reducing leakage in a high-performance deep-submicron instructioncache

摘要

Deep-submicron CMOS designs maintain high transistor switchingnspeeds by scaling down the supply voltage and proportionately reducingnthe transistor threshold voltage. Lowering the threshold voltagenincreases leakage energy dissipation due to subthreshold leakage currentneven when the transistor is not switching. Estimates suggest a five-foldnincrease in leakage energy in every future generation. In modernnmicroarchitectures, much of the leakage energy is dissipated in largenon-chip cache memory structures with high transistor densities. Whilencache utilization varies both within and across applications, modernncache designs are fixed in size resulting in transistor leakageninefficiencies. This paper explores an integrated architectural andncircuit-level approach to reducing leakage energy in instruction cachesn(i-caches). At the architecture level, we propose the DynamicallynResIzable i-cache (DRI i cache), a novel i-cache design that dynamicallynresizes and adapts to an application's required size. At thencircuit-level, we use gated-Vdd, a novel mechanism thatneffectively turns off the supply voltage to, and eliminates leakage in,nthe SRAM cells in a DRI i-cache's unused sections. Architectural andncircuit-level simulation results indicate that a DRI i-cachensuccessfully and robustly exploits the cache size variability bothnwithin and across applications. Compared to a conventional i-cache usingnan aggressively-scaled threshold voltage a 64 K DRI i-cache reduces onnaverage both the leakage energy-delay product and cache size by 62%,nwith less than 4% impact on execution time. Our results also indicatenthat a wide NMOS dual-Vt gated-Vdd transistor withna charge pump offers the best gating implementation and virtuallyneliminates leakage energy with minimal increase in an SRAM cell readntime area as compared to an i-cache with an aggressively-scalednthreshold voltage