Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers

摘要

Various 16-bit multiplier architectures are compared in terms of dissipated energy, propagation delay, energy-delay product (EDP), and area occupation, in view of low-power low-voltage signal processing for low-frequency applications. A novel practical approach has been set up to investigate and graphically represent the mechanisms of glitch generation and propagation. It is found that spurious activity is a major cause of energy dissipation in multipliers. Measurements point out that, because of its shorter full-adder chains, the Wallace multiplier dissipates less energy than other traditional array multipliers (8.2 $mu$ W/MHz versus 9.6 $mu$ W/MHz for 0.18-$mu$ m CMOS technology at 0.75 V). The benefits of transistor sizing are also evaluated (Wallace including minimum-size transistors dissipates 6.2 $mu$W/MHz). By combining transmission gates with static CMOS in a Wallace architecture, a new approach is proposed to improve the energy-efficiency further (4.7 $mu$W/MHz), beyond recently published low-power architectures. The innovation consists in suppressing glitches via resistance–capacitance low-pass filtering, while preserving unaltered driving capabilities. The reduced number of $V_{rm dd}$-to-ground paths also contributes to a significant decrease of static consumption.