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Design of Asynchronous Circuits for High Soft Error Tolerance in Deep Submicrometer CMOS Circuits

机译:深亚微米CMOS电路中具有高软错误容限的异步电路设计

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As the devices are scaling down, the combinational logic will become susceptible to soft errors. The conventional soft error tolerant methods for soft errors on combinational logic do not provide enough high soft error tolerant capability with reasonably small performance penalty. This paper investigates the feasibility of designing quasi-delay insensitive (QDI) asynchronous circuits for high soft error tolerance. We analyze the behavior of null convention logic (NCL) circuits in the presence of particle strikes, and propose an asynchronous pipeline for soft-error correction and a novel technique to improve the robustness of threshold gates, which are basic components in NCL, against particle strikes by using Schmitt trigger circuit and resizing the feedback transistor. Experimental results show that the proposed threshold gates do not generate soft errors under the strike of a particle within a certain energy range if a proper transistor size is applied. The penalties, such as delay and power consumption, are also presented.
机译:随着器件尺寸的缩小,组合逻辑将容易受到软错误的影响。用于组合逻辑上的软错误的常规软错误容忍方法不能以足够小的性能损失来提供足够高的软容错能力。本文研究了设计具有高软错误容忍度的准延迟不敏感(QDI)异步电路的可行性。我们分析了存在粒子罢工的空常规逻辑(NCL)电路的行为,并提出了一种用于软错误校正的异步流水线和一种新的技术来提高阈值门的鲁棒性,这是NCL中的基本组件,针对粒子使用施密特触发器电路调整反馈晶体管的大小。实验结果表明,如果应用适当的晶体管尺寸,则在一定能量范围内,提出的阈值门不会在粒子撞击下产生软错误。还介绍了诸如延迟和功耗之类的惩罚措施。

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