深亚微米CMOS电路多电源全芯片ESD技术研究

摘要

深亚微米CMOS电路具有器件特征尺寸小、复杂度高、面积大、数模混合等特点,电路全芯片ESD设计已经成为设计师面临的一个新的挑战.多电源CMOS电路全芯片ESD技术研究依据工艺、器件、电路三个层次进行,对芯片ESD设计关键点进行详细分析,制定了全芯片ESD设计方案与系统架构,该方案采用SMIC0.35 μm 2P4M Polycide混合信号CMOS工艺流片验证,结果为电路HBM ESD等级达到4500 V,表明该全芯片ESD方案具有良好的ESD防护能力.%CMOS circuit possesses small device feature size, unusual complexity, large chip area and Digital-model mixed-signals, etc. All these lead to a new challenge to chip designers in circuit ESD design. The Whole-Chip ESD for Multi-power Circuit is studied according to the analysis method of "process first,device then,circuit last" ,and are proposed and analysed in detail for design keys of ESD total solution. A whole-chip ESD protection solution and a whole-chip ESD protection composition is provided,its HBM ESD level reaches 4500V based on SMIC 0. 35 fim 2P4M Polycide mixed-signal CMOS process. The result indicates the whole-chip ESD protection solution possesses a good ESD ability.