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An Offset-Tolerant Dual-Reference-Voltage Sensing Scheme for Deep Submicrometer STT-RAM

机译:深亚微米STT-RAM的偏移容限双参考电压传感方案

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Due to the increased process variation and reduced supply voltage in deep submicrometer technology nodes, an offset-tolerant sensing scheme has become essential. However, most offset-tolerant sensing schemes suffer from inherent performance degradation owing to multiple-stage sensing. In this paper, a dual sensing scheme (DVSS) that selectively uses an optimal between and is proposed. This scheme is tolerant to process variations, and can be used as a spin-transfer-torque random access memory. Because of no additional sensing stage, the offset-tolerant sensing is achieved without sacrificing the performance. The optimal is selected after fabrication, and the calibrated switch control bit, which contains selection information, is stored permanently in an on-chip nonvolatile latch. Monte Carlo HSPICE simulation results, using an industry-compatible 45-nm model parameters, show that the proposed DVSS achieves a read yield of 98.24% for 32 Mb (6.1 sigma) with faster sensing speed and lower read energy per bit compared with the state-of-the-art offset-tolerant sensing scheme.
机译:由于深亚微米技术节点中工艺变化的增加和电源电压的降低,因此耐偏移的传感方案变得至关重要。然而,由于多级感测,大多数耐失调感测方案固有的性能下降。在本文中,提出了一种双感测方案(DVSS),该方案有选择地使用和之间的最优值。这种方案可以容忍过程变化,并且可以用作自旋转移转矩随机存取存储器。由于没有附加的感测阶段,因此可以在不牺牲性能的情况下实现耐偏量感测。最佳选择是在制造后选择的,包含选择信息的校准开关控制位被永久存储在片上非易失性锁存器中。使用行业兼容的45 nm模型参数进行的Monte Carlo HSPICE仿真结果表明,与该状态相比,所提出的DVSS在32 Mb(6.1 sigma)的情况下实现了98.24%的读取良率,具有更快的感测速度和更低的每位读取能量最先进的偏移容限传感方案。

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