A 5-MHz, 3.6-mW, 1.4-V SRAM with nonboosted, vertical bipolarbit-line contact memory cell

摘要

This paper describes a 256-Kbit SRAM fabricated using a novelnbipolar bit-line contact memory cell having a large static noise margin.nVertical PNP transistors are introduced at the bit-line contact area,nwhich realizes lower operational voltage and a memory-cell areanequivalent to a 4-NMOS-type cell. The minimum operating voltage is 1.4 Vnwithout using a boosting technique, and the access time is 60 ns at a Vncc of 1.8 V and room temperature. The power dissipation isn3.6 mW at a Vcc of 1.4 V. The operating Vcc rangenis 1.4-4.0 V