Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability

摘要

This paper presents a fast, low-power, binary carry-lookahead, 64-bit dynamic parallel adder architecture for high-frequency microprocessors. The adder core is composed of evaluate circuits and feedback reset chains implemented by self-resetting CMOS (SRCMOS) circuits with enhanced testability. A new tool, SRCMOS pulse analyzer (SPA), is developed for checking dynamic circuits for proper operation and performance. The nominal propagation delay and power dissipation of the adder were measured to be 1.5 ns (at 22/spl deg/C with V/sub dd/=2.5 V) and 300 mW. The adder core size is 1.6/spl times/0.275 mm/sup 2/. The process technology used was the 0.5 /spl mu/m IBM CMOS5X technology with 0.25 /spl mu/m effective channel length and five layers of metal. The circuit techniques are easily migratable to multigigahertz microprocessor designs.