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Fast edge triggered self-resetting CMOS receiver with parallel L1/L2 (master/slave) latch
Fast edge triggered self-resetting CMOS receiver with parallel L1/L2 (master/slave) latch
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机译:具有并行L1 / L2(主/从)锁存器的快速边沿触发自复位CMOS接收器
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摘要
A high speed self-resetting, edge-triggered CMOS (SRCMOS) receiver and parallel L1/L2 latch combination are provided which may be used to receive and latch data from a single-ended input of static random access memory (SRAM) or a dynamic random access memory (DRAM). The invention comprises a true/complement generator circuit (TCG) for generating a data and its complement from a single-ended input, a reset circuit for automatically resetting the TCG independent of the system clock, and a parallel L1/L2 latch for storing the data for further processing. The L1/L2 latch preferably has scan-in and scan-out ports useful for testing and diagnostic purposes.
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