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Analysis of bump resistance and current distribution of ultra-fine-pitch microbumps

机译:超细间距微凸点的凸点电阻和电流分布分析

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摘要

To keep up with the demand of continuous increase in device densities, the integration of three-dimensional integrated circuits (3D-1C) has become the most probable solution, and the utilization of ultra-fine-pitch microbump has emerged as an essential component of 3D-IC technology. In this study, a Kelvin bump structure was fabricated and resistances measured at different angles on a 20.0 urn microbump were investigated. The microbump resistance at 0°, 60°, 120°, and 180° are 74.7, 45.9, 14.6, and 13.7 mΩ, respectively. These high resistances in microbumps may result in high interconnect resistance and cause resistance/capacitance (RC) delay, and thus lower the electrical performance of 3D-IC. A series of finite-element-model (FEM) was built to analyze the distribution of electric field in microbump. The FEM results have shown that the current is distributed uniformly in the thin solder joint, but current crowding still occurs in the Cu under-bump-metallization (UBM). The finding of the current crowding in the Cu UBM is the main cause of high resistances in the microbump. Thickening the Al trace, for example, from 0.4 μm to 1.5 μm, is a direct solution to reduce the unexpected high microbump resistance. A numerical model which treated solder joints as a resistance network was also performed in this study. For comparison, both FEM and the numerical model show the same trend and agree with the measurement results from Kelvin bump structure. The results all point to one thing: thickening the Al trace turn out to be the most effective approach to reduce high microbump resistance. When the Al trace thickness is increased from 0.8 to 3.0 urn, the microbump resistance is decreased to half of the original value, resulted from the alleviation of current crowding in the Cu UBM.
机译:为了满足不断增加的器件密度的需求,三维集成电路(3D-1C)的集成已成为最可能的解决方案,而超细间距微凸点的使用已成为其必不可少的组成部分。 3D-IC技术。在这项研究中,制造了开尔文凸点结构,并研究了在20.0微米微凸点上以不同角度测量的电阻。 0°,60°,120°和180°的微凸点电阻分别为74.7、45.9、14.6和13.7mΩ。微凸块中的这些高电阻可能会导致高互连电阻并导致电阻/电容(RC)延迟,从而降低3D-IC的电气性能。建立了一系列有限元模型(FEM)来分析微凸点中的电场分布。有限元分析结果表明,电流在薄焊点中均匀分布,但在铜凸点下金属化(UBM)中仍然出现电流拥挤的情况。 Cu UBM中电流拥挤的发现是微凸点中高电阻的主要原因。直接将Al痕迹增厚(例如,从0.4μm增至1.5μm)是降低意料之外的高耐微凸点电阻的直接解决方案。在这项研究中,还建立了将焊点视为电阻网络的数值模型。为了进行比较,FEM和数值模型都显示出相同的趋势,并且与开尔文凸点结构的测量结果一致。结果全部表明一件事:加厚Al痕迹是降低高抗微凸点性能的最有效方法。当铝迹线厚度从0.8增至3.0微米时,抗微凸点电阻将降低至原始值的一半,这是由于缓解了铜UBM中的电流拥挤所致。

著录项

  • 来源
    《Microelectronics & Reliability》 |2013年第1期|41-46|共6页
  • 作者单位

    Department of Materials Science and Engineering, National Chiao Tung University, Hsin-chu 30010, Taiwan, ROC;

    Department of Materials Science and Engineering, National Chiao Tung University, Hsin-chu 30010, Taiwan, ROC;

    Department of Materials Science and Engineering, National Chiao Tung University, Hsin-chu 30010, Taiwan, ROC;

    Department of Materials Science and Engineering, National Chiao Tung University, Hsin-chu 30010, Taiwan, ROC;

    Introduction of Electronics & Optoelectronics Research Laboratories, Industrial Technology Research Institute, Hsin-chu, 31040 Taiwan, ROC;

    Introduction of Electronics & Optoelectronics Research Laboratories, Industrial Technology Research Institute, Hsin-chu, 31040 Taiwan, ROC;

    Introduction of Electronics & Optoelectronics Research Laboratories, Industrial Technology Research Institute, Hsin-chu, 31040 Taiwan, ROC;

    Research Center for Applied Sciences, Academia Sinica, Taipei, 11529 Taiwan, ROC;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
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