Analog-Based CMOS Duty Cycle Corrector with 50-800 MHz Operating Range

摘要

In this paper, a novel accurate analog-based 50% duty cycle corrector (DCC) for high-speed and high-resolution operations is presented. Due to the performance limitations of conventional DCCs, such as a confined locking range and overtone locking, a novel delay line using forward-body-bias technique and reset circuit are adopted to enlarge the locking range of the proposed DCC. Simulated results based on the standard 0.18 mu m 1.8V standard CMOS process show that output duty cycle error is less than +/- 1% over an input frequency range of 50-800 MHz. The peak-to-peak jitter at 800 MHz is 789.77 fs with a power consumption of 11.09 mW. The active layout area of the proposed DCC is 0.21 x 0.21 mm(2).