A differential 50%Duty Cycle Corrector for high speed sensor is proposed in this paper. Compared with the conventional analog duty-cycle detectors designed in CMOS process,the proposed circuit has a simple and robust ar-chitecture and proofs the possibility of clock duty cycle correction at frequencies as high as 4 GHz. The novel features include a duty cycle detector using continuous-time integrator with a low-pass pre-filter and clock buffers chain de-signed with Source-Coupled Logic. The Duty Cycle Corrector is designed under Chartered 0.18μm CMOS process and optimized for high-speed operation. The experimental results show that the circuit can work well at frequencies ranging from 500 MHz to 4.0 GHz and the acceptable input duty cycle range is 30%~70%. The power consumption is 5.37 mW and output jitter is 19.3 ps at 4GHz. The area of the test chip(include the probe pad)is 550μm×370μm.%提出了一种用于高速传感器的宽带差分50%占空比校准电路.与传统CMOS模拟占空比校准电路相比,所提出电路结构简单工作稳定,并且证明了该电路的最高校正频率可达4 GHz.所提出电路中的占空比检测器采用基于低通预滤波的连续时间积分器和带有源耦合逻辑结构的时钟缓冲器链.采用了0.18μm CMOS工艺,并针对高速应用条件进行了优化.实验结果表明,所提出电路在500 MHz至4.0 GHz频率范围内正常,可接受的输入占空比为30%~70%.在4 GHz输入信号条件下功耗为5.37 mW,输出抖动为19.3 ps.测试芯片面积为550μm×370μm.
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