TECHNIQUES FOR CALIBRATING 50 DUTY CYCLE DIFFERENTIAL FREQUENCY DOUBLER

摘要

A frequency doubler circuit is presented that provides a way to quickly and simply calibrate the phase delay required for a differential 50% output duty cycle frequency doubler in a manner that is low in cost and current drain. A fully differential approach is used, in which the components of a differential input signal are used to generate a differential output signal and a delayed differential output signal. The differential output signal and the delayed differential output signal are combined in the logic circuitry to determine the components of the differential double frequency output signal. Outputs of the logic circuitry are used to adjust the amount of delay in the delayed output signal so that the double frequency output signal has a duty cycle of 50%. In some embodiments, the positive and negative components of the delayed signal can be adjusted independently.