Optimization of Active Geometry Configuration and Shallow Trench Isolation (STI) Stress for Advanced CMOS Devices

摘要

Mechanical stress induced by active geometry is optimized for minimum variation of complementary metal oxide semiconductor (CMOS) electrical characteristics with varying active profiles. In this study, wafers with two different shallow trench isolation (STI) stress levels were investigated. By co-optimizing the active profile and STI stress level of model test structures, less than 3% device deviation is achieved when compared with simulation program with integrated circuit emphasis (SPICE) model in the full breadth of N channel and P channel metal oxide semiconductor (N/PMOS) geometry.