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>Impact Of Trench Sidewall Interface Trap In Shallow Trench Isolation On Junction Leakage Current Characteristics For Sub-0.25 /spl mu/m CMOS Devices
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Impact Of Trench Sidewall Interface Trap In Shallow Trench Isolation On Junction Leakage Current Characteristics For Sub-0.25 /spl mu/m CMOS Devices
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机译:低于0.25 / splμm/ m CMOS器件的浅沟槽隔离中的沟槽侧壁界面陷阱对结漏电流特性的影响