Development of Hard Mask Process on Magnetic Tunnel Junction for a 4-Mbit Magnetic Random Access Memory

摘要

To enlarge the read margin of magnetic random access memory (MRAM), we developed a SiO_2/Si_3N_4 hard mask process for magnetic tunnel junction (MTJ) stack patterning. This process can protect MTJ materials from oxidation during the resist removal process and reduces the distribution of MTJ resistance for 0.32-μm-wide bits on an 8-in.-diameter wafer more than the conventional process does. We also developed process integration for 4-Mbit toggle MRAMs: the read margin for 4-Mbit reached nearly 18σ.