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Corrections to “Copper Anisotropy Effects in Three-Dimensional Integrated Circuits Using Through-Silicon Vias”

机译：对“使用硅通孔的三维集成电路中的铜各向异性效应”的修正

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《Device and Materials Reliability, IEEE Transactions on》 |2012年第3期|p.582-582|共1页
作者
Karmarkar A. P.; Xu X.; Yeap K.-B.; Zschech E.;
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Synopsys (India) Private Ltd., Hyderabad, India;

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1. Copper Anisotropy Effects in Three-Dimensional Integrated Circuits Using Through-Silicon Vias [J] . Karmarkar A. P. Device and Materials Reliability, IEEE Transactions on . 2012,第2期

机译：使用硅通孔的三维集成电路中的铜各向异性效应
2. Effects of Copper Plasticity on the Induction of Stress in Silicon from Copper Through-Silicon Vias (TSVs) for 3D Integrated Circuits [J] . Benjamin Backes, Colin McDonough, Larry Smith, Journal of Electronic Testing: Theory and Applications: Theory and Applications . 2012,第1期

机译：铜可塑性对3D集成电路的硅通孔（TSV）中硅中应力诱导的影响
3. Effects of Copper Plasticity on the Induction of Stress in Silicon from Copper Through-Silicon Vias (TSVs) for 3D Integrated Circuits [J] . Benjamin Backes, Colin McDonough, Larry Smith, Journal of Electronic Testing . 2012,第1期

机译：铜可塑性对3D集成电路的硅通孔（TSV）中硅中应力诱导的影响
4. Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits [C] . Weerasekera Roshan, Grange Matt, Pamunuwa Dinesh, . 2009

机译：三维（3-D）集成电路中硅通孔（TSV）的紧凑建模
5. The Scaling and Microstructure Effects on the Thermal Stress and Reliability of Through-Silicon Vias in 3D Integrated Circuits [D] . Spinella, Laura Emilie. 2017

机译：对3D集成电路中通过硅通孔的热应力和可靠性的缩放和微观结构效应
6. Three-Dimensional Integrated Circuit (3D IC) Key Technology: Through-Silicon Via (TSV) [O] . Wen-Wei Shen, Kuan-Neng Chen 2017

机译：三维集成电路（3D IC）关键技术：硅通孔（TSV）
7. Three-Dimensional Integrated Circuit (3D IC) Key Technology: Through-Silicon Via (TSV) [O] . Wen-Wei Shen, Kuan-Neng Chen 2017

机译：三维集成电路（3D IC）关键技术：硅通孔（TSV）

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