New algorithms used in the GOALIE2 circuit extraction system are presented that are based on representing VLSI layout geometries as trapezoids. These include polygon-to-trapezoid decomposition, scanline management, and output sorting. The scanline algorithm virtually eliminates the redundant computation present in similar systems. It solves the VLSI layout analysis problem in O(n+k) expected time and O( square root n) expected space, where n is the total number of input segments and k is the total number of intersection points. The new scanline algorithm is robust in what it will maintain its performance over a wide range of layout styles. Experimental results show that the running time is O(n/sup 1.0547/), i.e. that these algorithms enable one to perform VLSI layout analysis in nearly linear time.
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