Design of Soft-Error-Aware SRAM With Multi-Node Upset Recovery for Aerospace Applications

摘要

To achieve improved speed of operation, a higher integration density and lower power dissipation, transistors are being scaled aggressively. This trend has reduced the critical charge of sensitive nodes. As a result, SRAM cells used in the high radiation environment of aerospace have become highly vulnerable to soft errors. In this paper, we propose a soft-error-aware 14T (SEA14T) SRAM cell for aerospace applications. The performance of the proposed cell is assessed by comparing it with other radiation-hardened SRAM cells like QUCCE12T, WE-QUATRO, RHM12T, RHD12T, RSP14T and RHBD14T. The proposed cell can fully recover from a single-event upset, of any strength and polarity, induced at all the sensitive nodes. Simulation results also show that SEA14T can fully recover from a multi-node upset induced at the internal node-pair. The proposed cell exhibits 1.06x/ 1.08x/ 1.36x shorter read delay than QUCCE12T/ WEQUATRO/ RHBD14T and 1.03x/ 1.09x/ 1.12x/ 1.15x/ 1.17x shorter write delay than RHM12T/ WE-QUATRO/ QUCCE12T/ RSP14T/ RHD12T. It also shows 1.33x/ 1.6x/ 2.4x higher read stability than QUCCE12T/ WE-QUATRO/ RHBD14T and 1.13x/ 1.32x/ 1.37x/ 1.42x/ 1.5x higher write ability than RHM12T/ WE-QUATRO/ QUCCE12T/ RSP14T/ RHD12T. Furthermore, the proposed cell consumes 2.31x/ 2.42x/ 2.55x/ 3.04x lower hold power than RHD12T/ RSP14T/ WE-QUATRO/ QUCCE12T @ V-DD = 1 V. All these improvements are achieved at the cost of a slightly larger area overhead.