Jitter Minimization in Digital PLLs with Mid-Rise TDCs

摘要

This paper analyzes the absolute jitter performance of digital phase-locked loops and compares the case when either a multi-bit time-to-digital converter with mid-rise characteristic or a bang-bang phase detector is adopted. The linear equivalent model of the PLL and expressions for random-noise and limit-cycle jitter are first derived for the case of a 2-bit time-to-digital converter with a mid-rise characteristic, and the optimal TDC resolution is determined. The analysis, which account for TDC mismatches, shows that, compared to the 1-bit one, the 2-bit time-to-digital converter can substantially reduce the quantization noise in the case of dominant random-walk noise at the TDC input. Moving to the bit midrise TDC case, the quantization noise can be further reduced at the cost of higher complexity and finer time resolution. The choice of 2 seems to be the best compromise between jitter reduction and complexity increase. Time-domain simulations assess the theoretical framework and demonstrate the validity of the assumptions made throughout the paper.