VLSI methodology for the design of RNS and QRNS full adder basedconverters

摘要

A unified graph-based methodology for designing VLSI residuennumber system (RNS) converters from binary system to RNS to quadraticnRNS (QRNS) and conversely, using full adders (FAs) as the basic buildingnblock, is introduced. The design procedure produces array architecturesnstarting from the algorithm bit level description of each converter andnending up with the hardware implementation, through a number of steps.nThese steps specify in a systematic way the minimum number of FAs fornperforming a conversion, as well as the interconnections among the FAs.nThey are implemented into a two-dimensional regular array processor andncharacterised by small hardware and area-time complexity, and highnthroughput rate, compared with existing implementations. The derivednarchitectures are generalised, covering a wide range of moduli and inputnbits