A VLSI design methodology for RNS full adder-based inner productarchitectures

摘要

In this paper, a systematic graph-based methodology fornsynthesizing VLSI RNS architectures using full adders as the basicnbuilding block is introduced. The design methodology derives arraynarchitectures starting from the algorithm level and ending up with thenbit-level design. Using as target architectural style the regular arraynprocessor, the proposed procedure constructs the two-dimensional (2-D)ndependence graph of the bit-level algorithm, which is formally describednby sets of uniform recurrent equations. The main characteristic of thenproposed architectures is that they can operate at very high-throughputnrates. The proposed architectures exhibit significantly reducedncomplexity over ROM-based ones