Energy-efficient design of digital circuits has become an important issue in recent years. In this work, the energy-efficient design methodologies are explored in 65nm, 45nm, 32nm and 22nm technology nodes. Those methodologies are applied to high performance VLSI adders to demonstrate their benefits in terms of energy and performance. Energy-delay estimation technique is used to estimate the delay and energy consumption of the designs. The result of the energy estimation depends on the switching activities at internal nodes of the micro-architecture. Formulas to calculate the switching factors of internal nodes for Kogge-Stone adder are derived. The use of average switching activity at all nodes is a quick and simple technique to be used in energy-delay estimation. The results of estimation with average switching activity are compared with Spice results. The comparison shows that the use of average switching activity is sufficiently precise method to be used in estimation. The proposed methodologies have resulted in the best design that can reduce the energy consumption over 50% as compared the commonly used adders in all interested technology nodes. The performance improvement is marginal(5--6%) in static designs and it is around 20% for dynamic designs.
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