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Reliability of SiO2 Gate Dielectric with Semi-Recessed Oxide Isolation

机译:SiO2栅电介质半隐式隔离的可靠性

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This paper reports the results of a study to minimize defects in the gate oxide and in the single crystal substrate of semi-recessed oxide (Semi-ROX) structures. It is shown that both an increase in oxidation mask thickness and a decrease in wet field oxidation temperature markedly reduce the incidence of low voltage breakdown in the gate oxide. Microscopic studies of samples which exhibited low voltage breakdown showed that the Si3N4 oxidation mask had failed to protect the surface of the region in which the gate oxide was grown. Semi-ROX processing also exhibited edge breakdown, most likely due to the Kooi effect (nitrided Si surface). The use of a thicker “pad” oxide and a decrease in the wet field oxide thickness were beneficial in reducing the magnitude of degradation in gate breakdown due to this edge effect.
机译:本文报告了一项研究结果,该研究可最大程度地减少半嵌入式氧化物(Semi-ROX)结构的栅极氧化物和单晶衬底中的缺陷。结果表明,增加氧化掩模的厚度和降低湿场氧化温度都可以显着降低栅氧化层中低压击穿的发生率。对表现出低压击穿的样品的显微研究表明,Si3N4氧化掩膜未能保护其中生长栅氧化物的区域的表面。半ROX加工也表现出边缘击穿,这很可能是由于Kooi效应(氮化的Si表面)引起的。使用较厚的“垫”氧化物和减小湿场氧化物的厚度有利于减少由于这种边缘效应而导致的栅极击穿退化的程度。

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