首页> 外文会议>Materials Research Society Symposium >Zr OXIDE BASED GATE DIELECTRICS WITH EQUIVALENT SiO2 THICKNESS OF LESS THAN 1.0 nm AND DEVICE INTEGRATION WITH Pt GATE ELECTRODE
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Zr OXIDE BASED GATE DIELECTRICS WITH EQUIVALENT SiO2 THICKNESS OF LESS THAN 1.0 nm AND DEVICE INTEGRATION WITH Pt GATE ELECTRODE

机译:ZR氧化物基栅电介质,等效SiO2厚度小于1.0nm,与Pt栅电极的器件集成

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摘要

ZrO2 films are investigated as an alternative to SiO2 gate dielectric below 1.5nm. A maximum accumulation capacitance approx 35 fF/ mu m~2 with a leakage current of less than 0.1 A/cm~2 has been achieved for a 3 nm Zr-O film, suggesting that ZrO2 can be scaled to below an equivalent oxide thickness of 0.5 nm. Al and Si doping is also investigated to reduce leakage currents and to increase the crystallization temperature of the film. Submicron MOSFETs with TiN or Pt gate electrodes have been fabricated with these gate dielectrics with excellent characteristics, demonstrating the feasibility of CMOS process integration. In particular, Pt damascene gate PMOS is shown to have the proper threshold voltage for dual metal gate CMOS application.
机译:将ZrO2薄膜作为SiO2栅极电介质的替代品进行研究,低于1.5nm。对于3nm Zr-O膜,已经实现了漏电流的最大累积电容,具有小于0.1a / cm〜2的漏电流,表明ZrO2可以缩放到低于等同的氧化物厚度0.5 nm。还研究了Al和Si掺杂以减少漏电流并增加薄膜的结晶温度。具有锡或PT栅电极的亚微米MOSFET已经用这些栅极电介质制造,具有优异的特性,展示了CMOS工艺集成的可行性。特别地,PT镶嵌栅极PMO被示出为双金属栅极CMOS应用具有适当的阈值电压。

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