Thermal and plasma treatments for improved (sub-)1 nm equivalent oxide thickness planar and FinFET-based replacement metal gate high-k last devices and enabling a simplified scalable CMOS integration scheme

摘要

We report on aggressively scaled replacement metal gate, higb-k last (RMG-HKL) planar and multi-gate fin field-effect transistor (FinFET) devices, systematically investigating the impact of post high-k deposition thermal (PDA) and plasma (SF_6) treatments on device characteristics, and providing a deeper insight into underlying degradation mechanisms. We demonstrate that: 1) substantially reduced gate leakage (J_G) and noise can be obtained for both type of devices with PDA and F incorporation in the gate stack by SF_6, without equivalent oxide thickness (EOT) penalty; 2) SF_6 enables improved mobility and reduced interface trapped charge density (N_(It)) down to narrower fin devices [fin width (W_(Fin))≥5nm], mitigating the impact of fin patterning and fin sidewall crystal orientations, while allowing a simplified dual-effective work function (EWF) CMOS scheme suitable for both device architectures; 3) PDA yields smaller, in absolute values, PMOS threshold voltage |V_T|, and substantially improved reliability behavior due to reduction of bulk defects.