首页> 外文期刊>IEEE Transactions on Components, Hybrids, and Manufacturing Technology >Electrical design technology for low dielectric constant multilayer ceramic substrate
【24h】

Electrical design technology for low dielectric constant multilayer ceramic substrate

机译:低介电常数多层陶瓷基板的电气设计技术

获取原文
获取原文并翻译 | 示例
       

摘要

A very important property of substrate materials for microelectronic packaging with high propagation speed is an appropriate dielectric constant. The VLSI demand will require even higher transmission speed on the substrate, and the use of an even lower dielectric constant material system. From the viewpoint of substrate propagation delays, the key factor for reducing signal propagation delays is hollow structure design between ground plane and signal plane, as well as the low dielectric constant material around signal lines. Another important factor for transmission properties is the ground plane design. Test samples of a new kind of packaging were made for estimation, and basic properties were measured. From this estimation, characteristics for a new kind of packaging substrate are summarized. As a result, this new structure substrate, with low dielectric constant, can be applied to high-speed VLSI packages in the future.
机译:具有高传播速度的用于微电子封装的衬底材料的非常重要的性质是适当的介电常数。 VLSI的需求将要求在基板上具有更高的传输速度,并使用更低的介电常数材料系统。从基板传播延迟的角度来看,减少信号传播延迟的关键因素是接地平面和信号平面之间的中空结构设计,以及信号线周围的低介电常数材料。传输特性的另一个重要因素是接地平面设计。制作了一种新型包装的测试样品以进行估计,并测量了基本性能。根据该估计,总结了新型包装基板的特性。结果,这种具有低介电常数的新型结构基板可在将来应用于高速VLSI封装。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号