High-speed VLSI interconnect modeling based on S-parameter measurements

摘要

A first-level-metal single-conductor IC interconnect model is developed for high-speed and high-density VLSI circuit design. The model shows interconnect circuit parameters that vary with frequency. Existing interconnect models exclude effects such as capacitive fringing and the influence of substrate conductance. The new model represents fine-line as well as wide-line interconnect behavior over a 20-GHz frequency range and includes these effects. The model parameters are compared to scattering parameter measurements as well as numerical simulations based on PISCES-II. Excellent agreement is shown with S-parameter measurements.