High-gain emitter inversion layer PNP vertical bipolar transistor in compensated CMOS technology

Jankovic N.D.

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High-gain emitter inversion layer PNP vertical bipolar transistor in compensated CMOS technology

机译：补偿CMOS技术中的高增益发射极反相层PNP垂直双极晶体管

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摘要

To improve the value of /spl beta/ of a pnp-merged vertical bipolar transistor (VET) in 'pseudo-BiCMOS' technology, a novel VBT design with an inversion layer-extended emitter is proposed. A high emitter injection efficiency of the forward-biased inversion layer is demonstrated in a pnp VET fabricated in 1 /spl mu/m compensated CMOS technology.

机译：为了提高“伪BiCMOS”技术中pnp合并的垂直双极晶体管（VET）的/ spl beta /值，提出了一种具有反转层扩展发射极的新颖VBT设计。在以1 / spl mu / m补偿的CMOS技术制造的pnp VET中，正向偏置层的发射极注入效率很高。

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《Electronics Letters》 |1998年第10期|P.984-985|共2页
作者
Jankovic N.D.;
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正文语种 eng
中图分类无线电电子学、电信技术;
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专利

1. Influence of the interfacial oxide layer on the gain of polycrystalline silicon emitter bipolar transistors processed in VLSI BiCMOS technology [J] . Giroult-Matlakowski G., Degors N. Electronics Letters . 1990,第14期

机译：界面氧化物层对在VLSI BiCMOS技术中处理的多晶硅发射极双极晶体管的增益的影响
2. High-Performance RF Mixer and Operational Amplifier BiCMOS Circuits Using Parasitic Vertical Bipolar Transistor in CMOS Technology [J] . Ilku Nam, Kwyro Lee IEEE Journal of Solid-State Circuits . 2005,第2期

机译：CMOS技术中使用寄生垂直双极晶体管的高性能RF混频器和运算放大器BiCMOS电路
3. AlGaAs/GaAs pnp heterojunction bipolar transistor with carbon-doped collector and emitter grown by atomic layer epitaxy [J] . Henderson T., Bayraktaroglu B. Electronics Letters . 1991,第9期

机译：原子层外延生长碳掺杂集电极和发射极的AlGaAs / GaAs pnp异质结双极晶体管
4. Simulation Study of Simple CMOS-Compatible Thin-SOI Vertical Bipolar Transistors on Thin BOX with an Inversion Collector [C] . Qiqing (Christine) Ouyang, Tak H. Ning International Conference on Simulation of Semiconductor Processes and Devices(SISPAD 2004); 20040902-04; Munich(DE) . 2004

机译：具有反转集电极的薄盒上简单兼容CMOS的薄SOI垂直SOI垂直双极晶体管的仿真研究
5. Realizing vertical bipolar transistors in a standard CMOS technology for the design of low-cost BiCMOS integrated circuits [D] . Rezaei, Farshid. 2004

机译：在标准CMOS技术中实现垂直双极晶体管，用于设计低成本BICMOS集成电路
6. Graphene-based lateral heterostructure transistors exhibit better intrinsic performance than graphene-based vertical transistors as post-CMOS devices [O] . Demetrio Logoteta, Gianluca Fiori, Giuseppe Iannaccone -1

机译：作为后CMOS器件基于石墨烯的横向异质结构晶体管表现出比基于石墨烯的垂直晶体管更好的固有性能
7. Fabrication And Electrical Characterization Of Silicon Bipolar Transistors In A O.5µm Based BiCMOS Technology.ud [O] . Abdul Rahim Alhan Farhanah, Abdul Rahim Ahmad Ismat, Hashim Md. Roslan, 2000

机译：基于O.5µm的BiCMOS技术中硅双极晶体管的制造和电特性。 ud
8. Evaluation of temperature-enhanced gain degradation of vertical npn and lateral pnp bipolar transistors [R] . Witczak, S. C. , Lacoe, R. C. , Galloway, K. F. 1997

机译：评估垂直npn和横向pnp双极晶体管的温度增强增益退化

High-gain emitter inversion layer PNP vertical bipolar transistor in compensated CMOS technology

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