Vertical PNP transistor in merged bipolar/CMOS technology

摘要

A vertical PNP structure for use in a merged bipolar/CMOS technology has a P+ buried layer (84) as a collector region, which is isolated from the P substrate (48) by an N- buried layer (82). The P+ buried layer (84) diffuses downwards into the N- buried layer (82) and upwards into a P- epitaxy layer (52d) and into a base region (54c). The base region (54c) is formed in the same processing step as the N well region (54b) of the PMOS transistor (42) and the collection region (54a) of the NPN transistor (40). By diffusing into the base region (54c), the width between the collector (84) and emitter (64e) is reduced. The emitter (64e) can be formed in conjunction with the source and drain regions of the PMOS transistor (42). The vertical PNP transistor (46) is laterally isolated from the other transistor devices by an annular ring formed from an N+ region (50c) formed in conjunction with an N+ DUF region (50a) used in the NPN transistor (40), and a N+ region (56b) formed in conjunction with an N+ collector region (56a) of the NPN transistor (40). An N+ DUF region (50b) may also be used in connection with the PMOS transistor (42).