Application of electrical effective channel length and external resistance measurement techniques to a submicrometer CMOS process

摘要

The practical applications and limitations of four methods for extracting the effective channel length (L/sub eff/) and series resistance (R/sub ext/) parameters for MOS devices are studied. The methods are: GD (gate drive) using fixed-current V/sub t/ or GD(I/sub ds/); SBGD (substrate-bias GD) using fixed-current V/sub t/ or SBGD (I/sub ds/); GD using maximum slope V/sub t/ or GD (G/sub m/); and SBGD using maximum slope V/sub t/ or SBGD (G/sub m/). Conventional and two LDD (lightly doped drain) structures fabricated in a submicrometer CMOS process are used. The results indicate that all the extraction methods are applicable to both n-channel and p-channel devices, although some are only valid over a small range of gate biases. Inconsistencies in applying V/sub t/ calculations to the extraction equations set a lower limit for V/sub gst/ of approximately 0.5 V, while the upper limit of 2.0-4.0 V arises due to imprecision in R/sub ds/ measurements influencing the double regression steps involved in the techniques. The SBGD (I/sub ds/) method was applicable over a wider range of bias conditions than the other techniques analyzed and is easier to implement.