Manufacturable Processes for ≤ 32-nm-node CMOS Enhancement by Synchronous Optimization of Strain-Engineered Channel and External Parasitic Resistances

摘要

Manufacturable processes to reduce both channel and external resistances $(R_{rm Ext})$ in CMOS devices are described. Simulations show that $R_{rm Ext}$ will become equivalent to strained Si channel resistance near the 32-nm logic node. Tensile stress in plasma-enhanced chemical-vapor-deposited $hbox{SiN}_{x}$ liners is increased with UV curing, boosting the NMOS drive current by 20% relative to a neutral reference. W contact-plug resistance $(R_{c})$ is reduced by 40% by optimizing preclean, liner/barrier, and nucleation steps. Replacing the fill material with Cu reduces $R_{c}$ by $>hbox{35}%$ as compared to W. The Schottky barrier height of silicide contacts to p-Si is reduced by 0.12 eV with a 10% addition of Pt, resulting in a $sim$10% increase in the PMOS drive current. By implementing a two-step anneal process $(hbox{spike} + hbox{laser})$, the source/drain-extension resistance can be reduced by 20%.