Application of self-aligned CoSi/sub 2/ interconnection in submicrometer CMOS transistors

摘要

CoSi/sub 2/ interconnection layers of 0.14-0.40- mu m thickness were applied in a self-aligned manner to 0.75- mu m-gate-length n-channel and p-channel transistors in a complete CMOS device fabrication flow. The sheet resistance above the active regions ranged from 1.6 to as low as 0.46 Omega /square for the four CoSi/sub 2/ thicknesses examined. Using an Al-Cu/TiW metallization, the resistance per contact for 1- mu m-diameter openings to CoSi/sub 2/ was >or=1 Omega . A junction consumption (due to silicide formation) of as great as approximately=80% for p/sup +/ (B) and approximately=90% for n/sup +/ (As)/p did not adversely affect the measured reverse-bias leakage for transistor gain performance. Furthermore, CoSi/sub 2/ layers were found compatible with the high-temperature annealing (902 degrees C) of an oxide overlayer, used to achieve some planarization of the device topography, without degradation in electrical performance.