A Combined Interface and Border Trap Model for High-Mobility Substrate Metal–Oxide–Semiconductor Devices Applied to and InP Capacitors

摘要

By taking into account simultaneously the effects of border traps and interface states, the authors model the alternating current capacitance–voltage ($C$– $V$) behavior of high-mobility substrate metal–oxide–semiconductor (MOS) capacitors. The results are validated with the experimental $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}/breakhbox{high-}kappa$ and InP/high-$kappa$ ( $C$–$V$) curves. The simulated $C$–$V$ and conductance–voltage ($G$– $V$) curves reproduce comprehensively the experimentally measured capacitance and conductance data as a function of bias voltage and measurement frequency, over the full bias range going from accumulation to inversion and full frequency spectra from 100 Hz to 1 MHz. The interface state densities of $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ and InP MOS devices with various high-$kappa$ dielectrics, together with the corresponding border trap density inside the high-$kappa$ oxide, were derived accordingly. The derived interface state densities are consistent to those previously obtained with other measurement methods-n-n. The border traps, distributed over the thickness of the high- $kappa$ oxide, show a large peak density above the two semiconductor conduction band minima. The total density of border traps extracted is on the order of $hbox{10}^{19} hbox{cm}^{-3}$. Interface and border trap distributions for InP and $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ interfaces with high-$kappa$ oxides show remarkable similarities on an energy scale relative to the vacuum reference.